|
@@ -141,13 +141,13 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
|
|
|
|
|
|
static inline u32 native_apic_msr_read(u32 reg)
|
|
|
{
|
|
|
- u32 low, high;
|
|
|
+ u64 msr;
|
|
|
|
|
|
if (reg == APIC_DFR)
|
|
|
return -1;
|
|
|
|
|
|
- rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
|
|
|
- return low;
|
|
|
+ rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
|
|
|
+ return (u32)msr;
|
|
|
}
|
|
|
|
|
|
static inline void native_x2apic_wait_icr_idle(void)
|
|
@@ -181,12 +181,12 @@ extern void enable_x2apic(void);
|
|
|
extern void x2apic_icr_write(u32 low, u32 id);
|
|
|
static inline int x2apic_enabled(void)
|
|
|
{
|
|
|
- int msr, msr2;
|
|
|
+ u64 msr;
|
|
|
|
|
|
if (!cpu_has_x2apic)
|
|
|
return 0;
|
|
|
|
|
|
- rdmsr(MSR_IA32_APICBASE, msr, msr2);
|
|
|
+ rdmsrl(MSR_IA32_APICBASE, msr);
|
|
|
if (msr & X2APIC_ENABLE)
|
|
|
return 1;
|
|
|
return 0;
|