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@@ -38,8 +38,6 @@
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/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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static struct clk r_clk = {
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- .name = "rclk",
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- .id = -1,
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.rate = 32768,
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};
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@@ -48,8 +46,6 @@ static struct clk r_clk = {
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* from the platform code.
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*/
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struct clk extal_clk = {
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- .name = "extal",
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- .id = -1,
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.rate = 33333333,
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};
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@@ -71,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
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};
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static struct clk dll_clk = {
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- .name = "dll_clk",
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- .id = -1,
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.ops = &dll_clk_ops,
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.parent = &r_clk,
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.flags = CLK_ENABLE_ON_INIT,
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@@ -96,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
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};
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static struct clk pll_clk = {
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- .name = "pll_clk",
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- .id = -1,
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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};
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@@ -211,6 +203,12 @@ static struct clk mstp_clks[] = {
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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static struct clk_lookup lookups[] = {
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+ /* main clocks */
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+ CLKDEV_CON_ID("rclk", &r_clk),
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+ CLKDEV_CON_ID("extal", &extal_clk),
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+ CLKDEV_CON_ID("dll_clk", &dll_clk),
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+ CLKDEV_CON_ID("pll_clk", &pll_clk),
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+
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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