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@@ -39,6 +39,7 @@
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#define RGMII_FER_RGMII(idx) (0x5 << ((idx) * 4))
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#define RGMII_FER_TBI(idx) (0x6 << ((idx) * 4))
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#define RGMII_FER_GMII(idx) (0x7 << ((idx) * 4))
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+#define RGMII_FER_MII(idx) RGMII_FER_GMII(idx)
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/* RGMIIx_SSR */
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#define RGMII_SSR_MASK(idx) (0x7 << ((idx) * 8))
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@@ -49,6 +50,7 @@
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static inline int rgmii_valid_mode(int phy_mode)
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{
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return phy_mode == PHY_MODE_GMII ||
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+ phy_mode == PHY_MODE_MII ||
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phy_mode == PHY_MODE_RGMII ||
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phy_mode == PHY_MODE_TBI ||
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phy_mode == PHY_MODE_RTBI;
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@@ -63,6 +65,8 @@ static inline const char *rgmii_mode_name(int mode)
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return "TBI";
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case PHY_MODE_GMII:
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return "GMII";
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+ case PHY_MODE_MII:
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+ return "MII";
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case PHY_MODE_RTBI:
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return "RTBI";
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default:
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@@ -79,6 +83,8 @@ static inline u32 rgmii_mode_mask(int mode, int input)
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return RGMII_FER_TBI(input);
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case PHY_MODE_GMII:
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return RGMII_FER_GMII(input);
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+ case PHY_MODE_MII:
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+ return RGMII_FER_MII(input);
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case PHY_MODE_RTBI:
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return RGMII_FER_RTBI(input);
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default:
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