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@@ -24,17 +24,25 @@
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* still in self-refresh is "not recommended", but seems to work.
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*/
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-static inline u32 sdram_selfrefresh_enable(void)
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+static inline void at91rm9200_standby(void)
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{
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- u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
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-
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- at91_sys_write(AT91_SDRAMC_LPR, 0);
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- at91_sys_write(AT91_SDRAMC_SRR, 1);
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- return saved_lpr;
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+ u32 lpr = at91_sys_read(AT91_SDRAMC_LPR);
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+
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+ asm volatile(
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+ "b 1f\n\t"
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+ ".align 5\n\t"
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+ "1: mcr p15, 0, %0, c7, c10, 4\n\t"
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+ " str %0, [%1, %2]\n\t"
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+ " str %3, [%1, %4]\n\t"
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+ " mcr p15, 0, %0, c7, c0, 4\n\t"
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+ " str %5, [%1, %2]"
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+ :
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+ : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91_SDRAMC_LPR),
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+ "r" (1), "r" (AT91_SDRAMC_SRR),
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+ "r" (lpr));
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}
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-#define sdram_selfrefresh_disable(saved_lpr) \
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- at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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+#define at91_standby at91rm9200_standby
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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#include <mach/at91sam9_ddrsdr.h>
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@@ -42,14 +50,12 @@ static inline u32 sdram_selfrefresh_enable(void)
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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-static u32 saved_lpr1;
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-
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-static inline u32 sdram_selfrefresh_enable(void)
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+static inline void at91sam9g45_standby(void)
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{
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- /* Those tow values allow us to delay self-refresh activation
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+ /* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1;
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- u32 saved_lpr0;
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+ u32 saved_lpr0, saved_lpr1;
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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@@ -63,14 +69,13 @@ static inline u32 sdram_selfrefresh_enable(void)
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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- return saved_lpr0;
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+ cpu_do_idle();
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+
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+ at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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+ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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-#define sdram_selfrefresh_disable(saved_lpr0) \
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- do { \
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- at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
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- at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
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- } while (0)
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+#define at91_standby at91sam9g45_standby
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#else
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#include <mach/at91sam9_sdramc.h>
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@@ -83,7 +88,7 @@ static inline u32 sdram_selfrefresh_enable(void)
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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-static inline u32 sdram_selfrefresh_enable(void)
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+static inline void at91sam9_standby(void)
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{
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u32 saved_lpr, lpr;
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@@ -92,11 +97,13 @@ static inline u32 sdram_selfrefresh_enable(void)
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
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AT91_SDRAMC_LPCB_SELF_REFRESH);
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- return saved_lpr;
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+
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+ cpu_do_idle();
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+
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+ at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
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}
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-#define sdram_selfrefresh_disable(saved_lpr) \
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- at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
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+#define at91_standby at91sam9_standby
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#endif
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